An active matrix display screen is diagrammatically constituted by two plates, the first being covered with a matrix of conductive blocks defining pixels, each block being associated with an addressing transistor controlled by addressing columns and lines, and the second plate being covered by a counter-electrode. A liquid crystal is inserted between the two plates.
Recently, active matrix display screens have appeared also including storage capacitors. The advantage of these capacitors is to limit temperature rise which, as regards a conventional screen, decreases the time constant of the capacity of the pixel, the liquid crystal and the control transistor becoming the center of leakage currents.
An example of active matrix display screens with storage capacitors is described in the document GB-A-2 115 199 in the article by D. TOMITA et al and entitled "A 6.5-in Diagonal TFT-LCD Module for Liquid Crystal TV" appearing in the journal SID 89 DIGEST, pp. 151-154, as well as in the article by Y. ASAI and entitled "A 6.7-in Square High-Resolution Full-Color TFL-LCD" appearing in the journal Japan Display 89, pp. 514-517.
FIGS. 1a and 1b and secondly 2a and 2b diagrammatically illustrate this prior art.
FIG. 1a shows a cell including a TFT transistor (this designation generally concerning a thin filmed transistor), and a Clc capacitor corresponding to the liquid crystal inserted between the armature of the first plate and the counter-electrode raised to a VCE potential. The addressing line controlling the grid of the TFT is given the reference L and the addressing column the reference C.
The cell of FIG. 1b differs from FIG. 1a by virtue of the presence of a storage capacitor Cs, one of its armatures being connected to the TFT and the other to a reference potential VR.
FIGS. 2a and 2b show two ways for controlling a screen with storage capacitors. In FIG. 2a, the storage capacitors corresponding to a given line Ln have one of their armatures connected to a dedicated electrode LC specially embodied for this purpose, all the lines LC being joined to a reference strip LR disposed on the side of the screen and brought to a potential VR. In FIG. 2b, the storage capacitors Cs belonging to a line Ln+1 have an armature connected to the preceding line Ln.
In the first case, the reference potential VR may be the potential of the counter-electrode. In the second, the reference potential is that of the preceding line. This potential is well-established and thus may serve as a reference during the frame time, except during the addressing time where its value is disturbed. As this disturbance occurs immediately before cooling of the line in question, it has no effect on the final potential of the pixel.
A large number of methods are possible for embodying such structures.
When it concerns conventional display screen without storage capacitors, the method is simpler than the one described in the document FR-A-2 533 072. This method, known as the "two level masking method", mainly includes the following operations:
preparation of a glass substrate by means of physico-chemical cleaning,
depositing a film of a transparent conductive material, such as tin and indium oxide (ITO),
first photoetching so as to give the transparent conductive film the shape of columns and blocks extended by a lengthening piece,
depositing a stacking formed of a semiconductive film, a nonconducting film and a metallic film,
second photoetching applied to the preceding stacking so as to define lines overlapping the lengthening pieces of the blocks and crossing the columns, this photoetching defining thin film transistors.
When it comes to embodying a screen with storage capacitors, this presents a special difficulty due to the embodiment of the armatures of the capacitors.
Known methods of embodiment require at least two masking levels and sometimes six. For example, in the technique described in the article by O. TOMITA et al mentioned earlier, a film of Mo-Ta is firstly deposited on a glass substrate and is subjected to a first photoetching so as to constitute the grids of the future transistors and one of the armatures of the storage capacitors. The unit is covered with a nonconductor. Then a film of ITO is deposited and a second photoetching is made so as to constitute the second armatures of the storage capacitors. Then a semiconductor (a-Si) is deposited and then this semiconductor is only allowed to be situated above the grids. Conductive films (a-Si n+, Mo/Al) are then deposited and etched during a fourth operation for masking and etching.